1. Field of the Invention
The present invention relates to interconnects and methods for forming them on semiconductor wafers. More particularly, the present invention relates to methods for reducing electromigration in interconnects.
2. Description of the Related Art
As integrated circuit devices grow smaller and smaller, higher conductance and lower capacitance is required of the interconnects. In order to accommodate these objectives, the trend has been towards the use of copper for interconnects and damascene methods for forming the interconnects. One drawback to the use of copper in the interconnects and metallization conductors is its tendency to diffuse (i.e., leakage) into adjacent dielectric layers. Copper diffuses easily into dielectric layers and diminishes the electrical insulation qualities of the dielectric.
To address these problems, copper barrier layers, for example layers containing tantalum, have been deposited before the deposition of copper to prevent “leakage”. This barrier layer must be able to prevent diffusion, exhibit low film resistivity, have good adhesion to dielectric and Cu and must also be CMP compatible. Also the layer must be conformal and continuous to fully encapsulate Cu lines with as thin a layer as possible. Due to higher resistivity of barrier material, the thickness should be minimized for Cu to occupy the maximum cross-sectional area. Failures due to electromigration are also major reliability concern affecting the backend interconnect reliability. Electromigration is the current induced diffusion of atoms due to the momentum transfer from moving electrons. Electromigration may result in voiding and thus open circuit failures.
Since copper has a much lower diffusivity through the grain boundary than aluminum, copper was felt to be intrinsically more reliable than aluminum by many orders of magnitude. This belief was one major motivation to migrate from aluminum based interconnects to copper based ones. In practice, however, copper/oxide based interconnects exhibit similar or only slightly better electromigration lifetimes compared to aluminum based interconnects.
This disparity between theoretical projections and observed characteristics has resulted from the misplaced notion that grain boundary diffusion is the dominant electromigration failure mechanism for both aluminum and copper wires. While this assumption may hold true for aluminum, it is not the case for copper.
Cu differs from Al in many ways. Since Copper is not well suited to subtractive formation processes such as dry-etch methods for the patterning of the lines, Cu is typically patterned by additive processes such as the Cu damascene process. In one such method, three sides of copper wire are wrapped in a refractory metal such as Ta, TaN, or combination thereof, to prevent diffusion of the copper into the oxide film. The fourth or top surface is covered by a dielectric film, such as SiN or SiC. The relatively weak bonding at the Cu and the dielectric layer interface in turn results in a strong propensity for interface diffusion during electromigration. It is believed that this diffusion path becomes the dominant factor in electromigration in almost all cases. That is, the electromigration lifetime is limited by the poor interface performance even with very high bulk copper properties.
Many methods have been proposed to solve these problems but typically the solutions offered create additional problems. For example, one proposed method involves the selective electroless deposition of metal such as CoWP on top of the Cu wire after copper chemical mechanical planarization (CMP). Although the electromigration lifetimes are improved, the method is very sensitive to the incoming wafer surface condition and the surface clean process. Furthermore, selective deposition may not be possible and may cause leakage and shorts between wires. This becomes worse as spacing between the wires becomes tighter. Extra process steps are required in performing the electroless deposition of metal on top of the copper wire as well as extra steps in cleaning the backside and bevel of the wafer. Moreover, the higher resistively of the capping metal may broaden the distribution of via resistance.
Accordingly, improved methods for forming thin metals on top of copper wires are needed. These methods should allow formation of the thin metal without adding extra process steps.